PM7367-PI datasheet(80/323 Pages) PMC

80 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.6.2 Task Priorities

The TMAC must perform a number of tasks concurrently in order to maintain a

steady flow of data through the system. The main tasks of the TMAC are

managing the Ready Queue (i.e. removing chains of data packets from the

queue and attaching them to the appropriate per-channel linked list) and

servicing requests for data from the Transmit Packet Interface. The priority of

service for each of the tasks is fixed by the TMAC as follows:-

· Top priority is given to servicing ‘expedited’ read requests from the Transmit

HDLC Processor / Partial Packet Buffer block (THDL).

· Second priority is given to removing chains of data packets from the TDRR

queue and attaching them to the appropriate per-channel linked list.

· Third priority is given to servicing non-expedited read requests from the

THDL.

8.6.3 DMA Transaction Controller

The DMA Transaction Controller coordinates the processing of requests from the

THDL with the reading of data stored in host memory. The reading of a data

packet may require a number of separate host memory transactions, interleaved

with transactions of other DMA channels. As well as reading data from the Host

Master Interface, the DMA Transaction Controller initiates read and write

transactions to the PCI Controller block (GPIC) for the purposes of maintaining

the data structures (queues, descriptors, etc.) in host memory.

8.6.4 Read Data Pipeline

The Read Data Pipeline inserts delay in the data stream between the GPIC

interface and the THDL interface to enable the DMA Transaction Controller to

generate appropriate control signals at the Transmit Packet Interface.

8.6.5 Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Transmit Channel

Descriptor Reference (TCDR) Table.

8.6.6 Free Queue Cache

The Free Queue Cache block implements the 6 element TDR Free Queue

cache. Caching TDRs reduces the number of host bus accesses that the TMAC

makes.

PM7367-PI Folha de dados(PDF) 80 Page - PMC-Sierra, Inc