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PM7367-PI Folha de dados(PDF) 95 Page - PMC-Sierra, Inc |
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PM7367-PI Folha de dados(HTML) 95 Page - PMC-Sierra, Inc |
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95 / 323 page ![]() PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 81 Register 0x004 : FREEDM-32P32 Master Interrupt Enable Bit Type Function Default Bit 31 to Bit 16 Unused XXXXH Bit 15 R/W TFUDRE 0 Bit 14 R/W IOCE 0 Bit 13 R/W TDFQEE 0 Bit 12 R/W TDQRDYE 0 Bit 11 R/W TDQFE 0 Bit 10 R/W RPDRQEE 0 Bit 9 R/W RPDFQEE 0 Bit 8 R/W RPQRDYE 0 Bit 7 R/W RPQLFE 0 Bit 6 R/W RPQSFE 0 Bit 5 R/W RFOVRE 0 Bit 4 R/W RPFEE 0 Bit 3 R/W RABRTE 0 Bit 2 R/W RFCSEE 0 Bit 1 R/W PERRE 0 Bit 0 R/W SERRE 0 This register provides interrupt enables for various events detected or initiated by the FREEDM. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. |
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