PM7347 datasheet(179/341 Pages) PMC

179 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

179

Document ID: PMC-1990267, Issue 3

PBS[2:0]

Data Status

010

The data byte read from the FIFO is the dummy byte that was written into the FIFO

when the HDLC abort sequence (01111111) was detected. This indicates that the data

link became inactive.

011

Unused.

100

The data byte read from the FIFO is the last byte of a normally terminated packet with

no CRC error and the packet received had an integer number of bytes.

101

The data byte read from the FIFO must be discarded because there was a non-integer

number of bytes in the packet.

110

The data byte read from the FIFO is the last byte of a normally terminated packet with

a CRC error. The packet was received in error.

111

The data byte read from the FIFO is the last byte of a normally terminated packet with

a CRC error and a non-integer number of bytes. The packet was received in error.

PKIN

The Packet In (PKIN) bit is logic one when the last byte of a non-aborted packet is written

into the FIFO. The PKIN bit is cleared to logic zero after the RDLC Status Register is read.

COLS

The Change of Link Status (COLS) bit is set to logic one if the RDLC has detected the

HDLC flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This

indicates that there has been a change in the data link status. The COLS bit is cleared to logic

zero by reading this register or by clearing the EN bit in the RDLC Configuration Register.

For each change in link status, a byte is written into the FIFO. If the COLS bit is found to be

logic one then the RDLC FIFO must be read until empty. The status of the data link is

determined by the PBS[2:0] bits associated with the data read from the RDLC FIFO.

OVR

The overrun (OVR) bit is set to logic one when data is written over unread data in the RDLC

FIFO buffer. This bit is not reset to logic zero until after the Status Register is read. While the

OVR bit is logic one, the RDLC and RDLC FIFO buffer are held in the reset state, causing

the COLS and PKIN bits to be reset to logic zero.

The FIFO buffer empty (FE) bit is set to logic one when the last RDLC FIFO buffer entry is

read. The FE bit goes to logic zero when the FIFO is loaded with new data.

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