PM7347 datasheet(175/341 Pages) PMC

175 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

175

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

Reserved

Bit 3

R/W

MEN

Bit 2

R/W

Bit 1

R/W

Bit 0

R/W

The EN bit controls the overall operation of the RDLC. When EN is set to logic one, RDLC

is enabled; when set to logic zero, RDLC is disabled. When RDLC is disabled, the RDLC

FIFO buffer and interrupts are all cleared. When RDLC is enabled, it will immediately begin

looking for flags.

Setting the terminate reception (TR) bit to logic one forces the RDLC to immediately

terminate the reception of the current data frame, empty the RDLC FIFO buffer, clear the

interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate

reception event in the same manner as it would the toggling of the EN bit from logic one to

logic zero and back to logic one. Thus, the RDLC state machine will begin searching for

flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself

to logic zero after the register write operation is completed and a rising and falling edge

occurs on the internal datalink clock input. If the RDLC Configuration Register is read after

this time, the TR bit value returned will be logic zero.

MEN

Setting the Match Enable (MEN) bit to logic one enables the detection and storage in the

RDLC FIFO of only those packets whose first data byte matches either of the bytes written to

the Primary or Secondary Match Address Registers, or the universal all-ones address. When

the MEN bit is logic zero, all packets received are written into the RDLC FIFO.

Setting the Match Mask (MM) bit to logic one ignores the PA[1:0] bits of the Primary

Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the

two least significant bits of the universal all-ones address when performing the address

comparison.

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