PM7347 datasheet(90/341 Pages) PMC

90 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

LOFINT[1:0]

The LOFINT[1:0] bits determine the integration period used for asserting and de-asserting E3

and DS3 LOF or J2 extended LOF on the FRMLOF register bit of the S/UNI-JET FRMR

LOF Status Register (x9CH) and on the FRMSTAT[4:1] output pins (if this function is

enabled by the STATSEL[2:0] register bits of the S/UNI-JET Configuration 2 Register). The

integration times are selected as shown in Table 9:

Table 9 LOF[1:0] Integration Period Configuration

LOFINT[1:0]

Integration Period

3 ms

2 ms

1 ms

Reserved

RFRM[1:0]

The RFRM[1:0] bits determine the expected frame structure of the received signal. Refer to

Table 10:

Table 10 RFRM[1:0] Receive Frame Structure Configurations

RFRM[1:0]

Expected Receive Frame Structure

DS3 (C-bit parity or M23 depending on the setting of the CBE bit in the DS3 FRMR

Configuration Register)

E3 (G.751 or G.832 depending on the setting of the FORMAT[1:0] bits in the E3

FRMR Framing Options Register)

J2 (G.704 and NTT compliant framing format)

DS1/E1/Arbitrary framing format (When EXT in the SPLR Configuration Register is

a logic zero, then DS1 or E1 direct-mapped or PLCP framing is selected (via the

PLCPEN and FORM[1:0] bits in the SPLR Configuration Register) and the frame

alignment is indicated by the ROHM[x] input pin. When EXT is a logic one, then the

arbitrary framing format is selected and overhead bit positions are indicated by the

ROHM[x] input pin.)

PM7347 Folha de dados(PDF) 90 Page - PMC-Sierra, Inc