PM7347 datasheet(89/341 Pages) PMC

89 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

R/W

RFRM[1]

Bit 6

R/W

RFRM[0]

Bit 5

R/W

LOFINT[1]

Bit 4

R/W

LOFINT[0]

Bit 3

R/W

RSCLKR

Bit 2

R/W

RCLKINV

Bit 1

R/W

RPOSINV

Bit 0

R/W

RNEGINV

The RNEGINV bit provides polarity control for input RNEG/RLCV/ROHM. When a logic

zero is written to RNEGINV, the input RNEG/RLCV/ROHM is not inverted. When a logic

one is written to RNEGINV, the input RNEG/RLCV/ROHM is inverted. The RNEGINV bit

setting does not affect the loopback data in diagnostic loopback.

RPOSINV

The RPOSINV bit provides polarity control for input RPOS/RDATI. When a logic zero is

written to RPOSINV , the input RPOS/RDATI is not inverted. When a logic one is written to

RPOSINV , the input RPOS/RDATI is inverted. The RPOSINV bit setting does not affect the

loopback data in diagnostic loopback.

RCLKINV

The RCLKINV bit provides polarity control for input RCLK. When a logic zero is written to

RCLKINV, RCLK is not inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are

sampled on the rising edge of RCLK. When a logic one is written to RCLKINV, RCLK is

inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are sampled on the falling edge

of RCLK.

RSCLKR

The RSCLKR bit is in effect only when the FRMRONLY bit in the S/UNI-JET Configuration

1 Register is set to logic one. When RSCLKR is a logic one, the RDATO, RFPO/RMFPO,

and ROVRHD outputs are updated on the rising edge of RSCLK. When RSCLKR is a logic

zero, the RDATO, RFPO/RMFPO, and ROVRHD outputs are updated on the falling edge of

RSCLK. If the RXGAPEN bit is a logic one, then RSCLKR affects RGAPCLK in the same

manner as it affects RSCLK.

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