PM7347 datasheet(324/341 Pages) PMC

Nome de Peças	PM7347

Descrição Electrónicos	SATURN USER NETWORK INTERFACE for J2/E3/T3

PDF	341 Pages

Scroll/Zoom	100%

Fabricante Electrônico	PMC [PMC-Sierra, Inc]

Página de início	http://www.pmc-sierra.com

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324 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

324

Document ID: PMC-1990267, Issue 3

Figure 76 Microprocessor Interface Write Timing

tH DW

Valid Data

D[7:0]

tVWR

tSAW

tH AW

tS DW

(CSB+W RB)

A[10:0]

Valid Address

ALE

tV L

tS ALW

tS LW

tH ALW

tHLW

Notes

A valid write cycle is defined as a logical OR of the CSB and the WRB signals.

In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW,

tHALW, tVL, tSLW, and tHLW are not applicable.

Parameter tHAW is not applicable if address latching is used.

When a set-up time is specified between an input and a clock, the set-up time is the time in

nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds

from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

PM7347 Folha de dados(PDF) 324 Page - PMC-Sierra, Inc