WM8591GEDSSLASHV datasheet(42/51 Pages) WOLFSON

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WM8591

Production Data

PD Rev 4.0 December 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ALC/Limiter Attack (gain ramp-down) Time

3:0

ATK[3:0]

0010

(33.6ms/

1ms)

ALC Mode:

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms…

(time doubles with every step)

1010 or higher: 8.6s

Limiter Mode:

0000: 250us

0001: 500us…

0010: 1ms

(time doubles with every step)

1010 or higher: 256ms

ALC/Limiter Decay (gain ramp up) Time

R18 (12h)

0011000

ALC Control 3

7:4

DCY[3:0]

1001

(17.15s/

614.4ms)

ALC Mode:

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms ….(time

doubles for every step)

1001: 17.15s

1010 or higher: 34.3s

Limiter Mode:

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….(time doubles

for every step)

1001: 614.4ms

1010 or higher: 1.2288s

Maximum Attenuation of PGA (Limiter only)

Limiter (attenuation below static)

0000 to 0011

-3dB

0100

-4dB

….

(-1dB steps)

1110

-14dB

R20 (14h)

0010100

Limiter

Control

3:0

MAXATTEN

[3:0]

0110

(-6dB)

1111

-15dB

MUTERA

Mute for Right Channel ADC:

0: Mute off

1: Mute on

MUTELA

Mute for Left Channel ADC:

0: Mute off

1: Mute on

R21 (15h)

0010101

ADC Mux

Control

LRBOTH

Right Channel Input PGA Controlled by Left Channel Register:

0: Right channel uses RAG and MUTERA

1: Right channel uses LAG and MUTELA

R23 (17h)

0010111

Software

Reset

[8:0]

RESET

Not reset

Writing any value to this register will apply a reset to the device

registers.

ADCSYNCEN

Enable the ADC Synchronizer:

0: Disabled

1: Enabled

3:2

BCLK_RATE

Set ADCBCLK and DACBCLK output rate in Master Mode:

00: BCLK = MCLK/4 (MCLK in DSP Mode)

01: BCLK = MCLK/4 (MCLK in DSP Mode)

10: BCLK = 64fs

11: BCLK = 128fs

ADCMCLK2DAC

Set both ADC and DAC to use ADCMCLK:

0: DAC uses DACMCLK

1: DAC uses ADCMCLK

R28 (1Ch)

0011100

ADC/DAC

Synchronization

ADCMCLKX2

Allows DAC synchronizer to synchronize to ADC operating at 2x

DAC rate:

0: Disabled

1: Enabled

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