SC1100 datasheet(88/348 Pages) NSC

88 / 348 page

www.national.com

Revision 1.1

SuperI/O Module (Continued)

Index 0Bh

RTC Control Register B - CRB (R/W)

Reset Type: Bit Specific

Width: Byte

Set Mode. This bit is reset at VPP power-up reset only.

0: Timing updates occur normally.

1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs.

Periodic Interrupt. Bits [3:0] of the CRA register determine the rate at which this interrupt is generated. It is cleared to 0 on

RTC reset (i.e., hardware or software reset) or when RTC is disable.

0: Disable.

1: Enable.

Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and

month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD register reads 0.

0: Disable.

1: Enable.

Update Ended Interrupt. This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware

or software reset) or when the RTC is disable.

0: Disable.

1: Enable.

Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is

always read as 0.

Data Mode. This bit is reset at VPP power-up reset only.

0: Enable BCD format.

1: Enable Binary format.

Hour Mode. This bit is reset at VPP power-up reset only.

0: Enable 12-hour format.

1: Enable 24-hour format.

Daylight Saving. This bit is reset at VPP power-up reset only.

0: Disable.

1: Enable:

- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.

- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.

Index 0Ch

RTC Control Register C - CRC (RO)

Reset Type: Bit Specific

Width: Byte

IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-

vate the interrupt pin), read the CRC register as the flag bits UF, AF and PF are cleared after reading this register.

0: IRQ inactive.

1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).

Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this

bit is cleared to 0 when this register is read.

0: No transition occurred on the selected tap since the last read.

1: Transition occurred on the selected tap of the divider chain.

Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD register reads 0. In addition, this bit is cleared to 0 when this

0: No alarm detected since the last read.

1: Alarm condition detected.

Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition,

this bit is cleared to 0 when this register is read.

0: No update occurred since the last read.

1: Time registers updated.

3:0

Reserved.

Table 4-18. RTC Registers (Continued)

Bit

Description

SC1100 Folha de dados(PDF) 88 Page - National Semiconductor (TI)

SC1100 Folha de dados(HTML) 88 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL