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Revision 1.1

SuperI/O Module (Continued)

4.3

CONFIGURATION STRUCTURE / ACCESS

This section describes the structure of the configuration

registers.

4.3.1

Index-Data Register Pair

The SIO configuration access is performed via an Index-

Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined

according to the state of the IO_SIOCFG_IN bit field of the

Core Logic module (F5BAR0+I/O Offset 00h[26:25]). Table

4-1 shows the selected base addresses as a function of the

IO_SIOCFG_IN bit field.

The Index register is an 8-bit R/W register located at the

selected base address (Base+0). It is used as a pointer to

the configuration register file, and holds the index of the

configuration register that is currently accessible via the

Data register. Reading the Index register returns the last

value written to it (or the default of 00h after reset).

The Data register is an 8-bit virtual register, used as a data

path to any configuration register. Accessing the data reg-

ister results with physically accessing the configuration reg-

ister that is currently pointed by the Index register.

4.3.2

Banked Logical Device Registers

Each functional block is associated with a Logical Device

Number (LDN). The configuration registers are grouped

into banks, where each bank holds the standard configura-

tion registers of the corresponding logical device. Table 4-2

shows the LDNs of the device functional blocks.

Figure 4-3 shows the structure of the standard PnP config-

uration register file. The SIO Control and Configuration reg-

isters are not banked and are accessed by the Index-Data

cal Device Control and Configuration registers are dupli-

cated over four banks for four logical devices. Therefore,

accessing a specific register in a specific bank is performed

by two-dimensional indexing, where the LDN register

selects the bank (or logical device), and the Index register

selects the register within the bank. Accessing the Data

higher results in a physical access to the Logical Device

Configuration registers currently pointed to by the Index

the LDN register.

Figure 4-3. Structure of the Standard

Configuration Register File

Table 4-1. SIO Configuration Options

IO_SIOCFG_IN

Settings

I/O Address

Description

Index

Data

SIO disabled

Configuration

access disabled

002Eh

002Fh

Base address 1

selected

015Ch

015Dh

Base address 2

selected

Table 4-2. LDN Assignments

LDN

Functional Block

00h

Real Time Clock (RTC)

01h

System Wakeup Control (SWC)

02h

Infrared Communication Port (IRCP)

05h

ACCESS.bus 1 (ACB1)

06h

ACCESS.bus 2 (ACB2)

08h

Serial Port

07h

20h

30h

60h

75h

FEh

Logical Device Number Register

SIO Configuration Registers

Logical Device Control Register

Standard Logical Device

Banks

(One per Logical Device)

2Fh

F0h

Bank

63h

74h

70h

71h

Standard Registers

Special (Vendor-defined)

Configuration Registers

Logical Device

Select

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