UCD3138064RGCR datasheet(65/104 Pages) TI

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Here is an overview of the key PSFB signals:

3 A – QB1

( DPWM1C )

3 B – QT1

( DPWM2 C)

2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN)

0 B –

QSYN 2,4

1 B –

QSYN 1 ,3

Transformer

Voltage

X1 , X2 , X 3 and Y1 , Y2 , Y 3

are sets of moving edges

All other edges are fixed .

DPWM 2 AF

DPWM 2 BF

DPWM3 AF

DPWM3 BF

Current

Peak Level

Figure 10-3. Key PSFB Signals

10.2.2.2.1 DPWM Synchronization

DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to

DPWM2, ½ period out of phase using these commands:

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave

Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;

LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1;

LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2;

// Slave to dpwm-0

// Slave to dpwm-1

// Slave to dpwm-2

If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code

examples are taken from the PSFB EVM code, unless otherwise stated.

10.2.2.3 Fixed Signals to Bridge

The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are used for

these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown in Figure 10-4.

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UCD3138064

SLUSB72D – MARCH 2013 – REVISED APRIL 2021

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