
PRELIMINARY
Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers
CYW2338
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 6, 2001, rev. **
12338\CYW2338
Features
• Operating voltage 2.7V to 5.5V
• Operating frequency to 2.5 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
• Lock detect feature
• Power-down mode ICC < 1 µA typical at 3.0V
• Serial data input accepts data clock rates as low as
1kHz
• Low power/voltage operation with low current standby
mode
• On-chip reference oscillator
• Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
• Available in a 24-pin CSP (Chip Scale Package)
• Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2338 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The CYW2338 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.5-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 27 mW.
Dual PLL Block Diagram
Pin Configuration
Binary 7-Bit
Prescaler
Phase
Detector
19-Bit
Pwr-dwn
Swallow Counter
Binary 11-Bit
Programmable Counter
64/65 or
Latch
PLL1
20-Bit Latch
20-Bit Latch
Prescaler
64/65 or
Cntrl 22-Bit
Shift
Reg.
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Pwr-dwn
Latch
PLL2
15-Bit
Reference Counter
15-Bit
Reference Counter
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Charge
Pump
Power
Control
Selector
GND (17)
VP2 (19)
GND (14)
GND (4)
GND (7)
VCC1 (1)
VCC2 (20)
FIN1 (5)
FIN1# (6)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
FIN2 (16)
FIN2# (15)
VP1 (2)
DOPLL1 (3)
FO/LD (10)
DOPLL2 (18)
Latch
Selector
fp1
fr1
fr2
fp2
128/129
128/129
VCC2
VP2
DOPLL2
GND
FIN2
FIN2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
VCC1
VP1
DOPLL1
GND
FIN1
FIN1#
GND
OSC_IN
OSC_OUT
FO/LD
1
2
3
4
5
6
7
8
9
10
(Top View)
1
2
3
4
5
15
14
13
12
11
DoPLL1
GND
Fin1
Fin1#
GND
GND
Fin2
Fin2#
GND
LE
(Top View)
4
5
6
7
19
18
17
16
15
3
DoPLL1
GND
Fin1
Fin1#
GND
GND
Fin2
Fin2#
GND
LE
2
1
NC
Vp1
8
9
OSC_IN
NC
14
13
DATA
NC
21
20
NC
DoPLL2
TSSOP
CSP
MLF
OSC_OUT (9)