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AX58200BI Folha de dados(PDF) 8 Page - ASIX Electronics Corporation

Nome de Peças AX58200BI
Descrição Electrónicos  EtherCAT Slave Controller SoC
PDF  180 Pages
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Fabricante Electrônico  ASIX [ASIX Electronics Corporation]
Página de início  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX58200BI Folha de dados(HTML) 8 Page - ASIX Electronics Corporation

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AX58200
EtherCAT Slave Controller SoC
List of Figures
FIGURE 1.1-1: AX58200 TYPICAL APPLICATIONS DIAGRAM............................................................................................ 2
FIGURE 1.2-1: AX58200 BLOCK DIAGRAM .................................................................................................................... 12
FIGURE 1.3-1: AX58200 PINOUT DIAGRAM ................................................................................................................... 13
FIGURE 2.1-1:CORTEX® -M4 BLOCK DIAGRAM .............................................................................................................. 32
FIGURE 2.2-1: SYSTEM RESET SOURCES......................................................................................................................... 36
FIGURE 2.2-2: NRESET RESET WAVEFORM................................................................................................................... 38
FIGURE 2.2-3: POWER-ON RESET (POR) WAVEFORM..................................................................................................... 38
FIGURE 2.2-4: LOW VOLTAGE RESET (LVR) WAVEFORM.............................................................................................. 39
FIGURE 2.2-5: BROWN-OUT DETECTOR (BOD) WAVEFORM .......................................................................................... 40
FIGURE 2.2-6: POWER DISTRIBUTION DIAGRAM............................................................................................................. 41
FIGURE 2.2-7: POWER MODE STATE MACHINE .............................................................................................................. 43
FIGURE 2.2-8: POWER DISTRIBUTION DIAGRAM............................................................................................................. 46
FIGURE 2.2-9: SRAM BLOCK DIAGRAM ........................................................................................................................ 49
FIGURE 2.2-10: SRAM MEMORY ORGANIZATION.......................................................................................................... 50
FIGURE 2.2-11: BUS MATRIX DIAGRAM ......................................................................................................................... 51
FIGURE 2.3-1: CLOCK GENERATOR GLOBAL VIEW DIAGRAM......................................................................................... 56
FIGURE 2.3-2: CLOCK GENERATOR BLOCK DIAGRAM.................................................................................................... 57
FIGURE 2.3-3: SYSTEM CLOCK BLOCK DIAGRAMS......................................................................................................... 58
FIGURE 2.3-4: HXT STOP PROTECT PROCEDURE............................................................................................................ 59
FIGURE 2.3-5: SYSTICK CLOCK CONTROL BLOCK DIAGRAM ......................................................................................... 59
FIGURE 2.3-6: CLOCK OUTPUT BLOCK DIAGRAM........................................................................................................... 60
FIGURE 2.3-7: USB CLOCK SOURCE............................................................................................................................... 61
FIGURE 2.3-8:HXT CLOCK SOURCE ............................................................................................................................... 62
FIGURE 2.26-1: SPI MASTER MODE APPLICATION BLOCK DIAGRAM............................................................................. 84
FIGURE 2.26-2: SPI SLAVE MODE APPLICATION BLOCK DIAGRAM ............................................................................... 84
FIGURE 2.27-1: I2C BUS TIMING..................................................................................................................................... 85
FIGURE 2.43-1: ESC SUB-SYSTEM BLOCK DIAGRAM ................................................................................................... 103
FIGURE 3.5-1: POWER ON RESET (POR) TIMING DIAGRAM ......................................................................................... 131
FIGURE 3.10-1: POWER-UP SEQUENCE TIMING DIAGRAM ............................................................................................ 142
FIGURE 3.11-1 I2C TIMING DIAGRAM ........................................................................................................................... 143
FIGURE 3.11-2 SPI MASTER MODE TIMING DIAGRAM ................................................................................................. 144
FIGURE 3.11-3 SPI SLAVE MODE TIMING DIAGRAM .................................................................................................... 146
FIGURE 3.11-4 I2S MASTER MODE TIMING DIAGRAM ................................................................................................. 147
FIGURE 3.11-5 I2S SLAVE MODE TIMING DIAGRAM ..................................................................................................... 148
FIGURE 3.11-6 I2C TIMING DIAGRAM ........................................................................................................................... 149
FIGURE 3.11-7 SPI MASTER MODE TIMING DIAGRAM ................................................................................................. 150
FIGURE 3.11-8 SPI SLAVE MODE TIMING DIAGRAM .................................................................................................... 152
FIGURE 3.11-9 RMII INTERFACE TIMING DIAGRAM..................................................................................................... 153
FIGURE 3.11-10 ETHERNET PHY MANAGEMENT INTERFACE TIMING DIAGRAM.......................................................... 154
FIGURE 3.11-11 SDIO DEFAULT MODE......................................................................................................................... 154
FIGURE 3.11-12 SDIO HIGH-SPEED MODE .................................................................................................................... 156
FIGURE 3.11-13: WRITE ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS) .......................................................... 156
FIGURE 3.11-14: WRITE ACCESS (2 ADDRESS BYTES, 32 KBIT - 4 MBIT EEPROMS).................................................... 157
FIGURE 3.11-15: READ ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS)............................................................ 157
FIGURE 3.11-16: PORT 2 MII TX TIMING DIAGRAM..................................................................................................... 158
FIGURE 3.11-17: PORT 2 MII RX TIMING DIAGRAM .................................................................................................... 159
FIGURE 3.11-18: MDC/MDIO WRITE ACCESS ............................................................................................................. 160
FIGURE 3.11-19: MDC/MDIO READ ACCESS............................................................................................................... 160
FIGURE 3.11-20: LATCH TIMING ................................................................................................................................. 161
FIGURE 3.11-21: SYNC TIMING.................................................................................................................................... 161
FIGURE 3.11-22: DIGITAL INPUT: INPUT DATA SAMPLED AT SOF, IO CAN BE READ IN THE SAME FRAME .................... 162
FIGURE 3.11-23: DIGITAL INPUT: INPUT DATA SAMPLED WITH LATCH_IN................................................................. 162
FIGURE 3.11-24: DIGITAL OUTPUT TIMING................................................................................................................... 162
FIGURE 3.11-25: OE_EXT TIMING ............................................................................................................................... 162
FIGURE 3.11-26: BASIC MOSI/MISO TIMING .............................................................................................................. 164



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