AX58200BI datasheet(9/180 Pages) ASIX

9 / 180 page

AX58200

EtherCAT Slave Controller SoC

FIGURE 3.11-27: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 1 BYTE READ DATA) WITH WAIT STATE BYTE . 165

FIGURE 3.11-28: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 2 BYTE READ DATA) WITH WAIT STATE BYTE . 166

FIGURE 3.11-29: PDI SPI SLAVE WRITE ACCESS (2 BYTE ADDRESSING, 1 BYTE WRITE DATA)...................................... 167

FIGURE 3.11-30: PDI SPI SLAVE WRITE ACCESS (3 BYTE ADDRESSING, 1 BYTE WRITE DATA)...................................... 168

FIGURE 3.11-31: FUNCTION SPI SLAVE WITH SHARE PIN TIMING DIAGRAM ................................................................ 169

FIGURE 3.11-32: FUNCTION SPI SLAVE WITH INDIVIDUAL PIN TIMING DIAGRAM ........................................................ 169

FIGURE 3.11-33: PWMX TIMING.................................................................................................................................. 170

FIGURE 3.11-34: ONLY PWM CHANNEL 2 SHIFT DIAGRAM ......................................................................................... 171

FIGURE 3.11-35: BBM (BREAK BEFORE MAKE) TIMING DIAGRAM ............................................................................. 172

FIGURE 3.11-36: ONE SHOT WITH MULTI STEP TIMING DIAGRAM ................................................................................ 172

FIGURE 3.11-37: ABZ TIMING DIAGRAM ..................................................................................................................... 173

FIGURE 3.11-38: CW/CCW TIMING DIAGRAM............................................................................................................. 173

FIGURE 3.11-39: CLK/DIR TIMING DIAGRAM ............................................................................................................. 173

FIGURE 3.11-40: HALL TIMING DIAGRAM .................................................................................................................... 173

FIGURE 3.11-41: SPI MASTER TIMING ......................................................................................................................... 175

FIGURE 3.11-42: MMISO /MMOSIO TIMING .............................................................................................................. 175

FIGURE 3.11-43: SPI MDRLD READY TIMEOUT TIMING ............................................................................................. 176

FIGURE 3.11-44: SPI MTRG TRIGGER PULSE TIMEOUT............................................................................................... 176

FIGURE 3.11-45: SPI MDRLD TRIGGER LDAC GAP AND WIDTH TIMING................................................................... 176

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