AX58200BI datasheet(10/180 Pages) ASIX

10 / 180 page

AX58200

EtherCAT Slave Controller SoC

List of Tables

TABLE 2.2-1: RESET VALUE OF REGISTERS .................................................................................................................... 37

TABLE 2.2-2: POWER MODE TABLE................................................................................................................................ 42

TABLE 2.2-3: POWER MODE DIFFERENCE TABLE ........................................................................................................... 42

TABLE 2.2-4: POWER MODE DEFINITION TABLE ............................................................................................................ 43

TABLE 2.2-5: CLOCKS IN POWER MODES....................................................................................................................... 44

TABLE 2.2-6: RE-ENTERING POWER-DOWN MODE CONDITION ...................................................................................... 46

TABLE 2.2-7: ADDRESS SPACE ASSIGNMENTS FOR ON-CHIP CONTROLLERS.................................................................. 49

TABLE 2.16-1: UART FEATURES ................................................................................................................................... 75

TABLE 2.42-1: PERIPHERALS INTERCONNECT MATRIX TABLE ....................................................................................... 98

TABLE 2.43-1: ESC BOOTSTRAP PINS CONFIGURATION ............................................................................................... 104

TABLE 2.43-2: ESC I2C EEPROM LAYOUT ................................................................................................................. 107

TABLE 2.43-3: ESC MEMORY MAP .............................................................................................................................. 118

TABLE 2.43-4: ESC FUNCTION REGISTER MAP ............................................................................................................ 120

TABLE 2.43-5: ESC MEMORY AND FUNCTION REGISTERS MIRROR MAPPING TABLE .................................................. 122

TABLE 3.5-1: POWER ON RESET (POR) TIMING TABLE................................................................................................ 132

TABLE 3.9-1: POWER CONSUMPTION............................................................................................................................ 141

TABLE 3.9-2: THERMAL CHARACTERISTICS ................................................................................................................. 141

TABLE 3.10-1: POWER-UP SEQUENCE TIMING TABLE................................................................................................... 142

TABLE 3.11-1: I2C EEPROM TIMING TABLE ............................................................................................................... 158

TABLE 3.11-2: PORT 2 MII TX TIMING TABLE............................................................................................................. 158

TABLE 3.11-3: PORT 2 MII RX TIMING TABLE............................................................................................................. 159

TABLE 3.11-4: MDC/MDIO TIMING TABLE................................................................................................................. 160

TABLE 3.11-5: DC SYNC/LATCH TIMING CHARACTERISTICS .................................................................................... 161

TABLE 3.11-6: DIGITAL I/O TIMING TABLE .................................................................................................................. 163

TABLE 3.11-7: PDI SPI SLAVE TIMING TABLE............................................................................................................. 164

TABLE 3.11-8: FUNCTION SPI WITH SHARE PIN TIMING TABLE .................................................................................... 169

TABLE 3.11-9: FUNCTION SPI WITH INDIVIDUAL PIN TIMING TABLE............................................................................ 169

TABLE 3.11-10: PWMX TIMING TABLE........................................................................................................................ 170

TABLE 3.11-11: PWMX SHIFT TIMING TABLE ............................................................................................................. 171

TABLE 3.11-12: PWMX BBM TIMING TABLE .............................................................................................................. 172

TABLE 3.11-13: STEP FUNCTION TIMING TABLE............................................................................................................ 172

TABLE 3.11-14: INCREMENTAL AND HALL ENCODER TIMING TABLE........................................................................... 174

TABLE 3.11-15: SPI MASTER TIMING TABLE ............................................................................................................... 177

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