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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AX58200BI Folha de dados(PDF) 1 Page - ASIX Electronics Corporation |
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AX58200BI Folha de dados(HTML) 1 Page - ASIX Electronics Corporation |
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1 / 180 page  1 AX58200 EtherCAT Slave Controller SoC Released Date: 11/22/2019 TEL: +886-3-579-9500 FAX: +886-3-579-9558 https://www.asix.com.tw/ ASIX Electronics Corporation 4F, No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan 30078 Features ARM® Cortex® -M4 processor, running up to 192 MHz Built-in Memory Protection Unit (MPU) Built-in Nested Vectored Interrupt Controller (NVIC) Hardware IEEE 754 compliant Floating-point Unit (FPU) DSP extension with hardware divider and single-cycle 32-bit hardware multiplier On-chip Memory Dual bank 512 KB Flash size (APROM) for Over-The-Air (OTA) upgrade On-chip Flash programming with In-Chip Programming (ICP), In-System Programming (ISP) and In-Application Programming (IAP) On-chip 160 KB SRAM 4 KB on-chip Flash for user-defined loader (LDROM) 4 KB non-readble Security Protection ROM (SPROM) Boot Loader Factory pre-loaded 32 KB mask ROM for secure boot procedure Uses SHA-256 and AES-256 to validate data in on-chip Flash and external SPI Flash ISP for firmware upgrade via UART and high speed USB device Timers Supports four sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter Supports twenty-four sets of 16-bit PWM counters Supports 18-bit free running watchdog timer counter Two Quadrature Encoder Interface (QEI) phase inputs (QEI_A, QEI_B) and one Index input (QEI_INDEX) Supports one Enhanced Capture (ECAP) channels Analog Interfaces One 12-bit, 16-ch 5 MSPS SAR ADC Two 12-bit, 1 MSPS voltage type DAC Two rail-to-rail Analog Comparators Two Operational Amplifiers with 0~AVDD input voltage range. Communication Interfaces One USB 2.0 High Speed OTG with on-chip transceiver One IEEE Std. 802.3 10/100Mbps Ethernet MAC with RMII Up to 6 sets of UARTs Three sets of ISO-7816-3 Three sets of I2C devices with Master/Slave mode One SPI Master supports maximum 32 MB external SPI Flash memory One set of Quad-SPI controller with Master/Slave mode One set of I2S interface with Master/Slave mode Two sets of USCI, configured as UART, SPI or I2C function Two sets of CAN 2.0B controllers Two sets of Secure Digital Host Controllers, compliant with SD Memory Card Specification Version 2.0. Supports Hardware ECC, AES, DES, 3DES, SHA, HMAC accelerator cryptography engineers Supports Real-Time Clock Built-in Die Temperature Sensor (DTS) with 1℃ resolution EtherCAT Slave Controller (ESC) Sub-system 2 Integrated Fast Ethernet PHYs 3rd Ethernet MII Port for flexible EtherCAT network configuration 8 Fieldbus Memory Management Units (FMMUs) 8 Sync Managers 64-bit distributed clock support allows synchronization with other EtherCAT devices 9K bytes RAM Step & Direction Controller Incremental and Hall Encoder Interface SPI Master Controller Emergency Stop Input Configurable Watchdog for Outputs and Inputs Monitoring Integrates On-chip Power-on Reset Circuit 144-pin HSFBGA 10x10 mm, 0.8-mm pitch, RoHS Compliant Package Operating Temperature Range: -40 to +85°C, -40 to +105°C Document No: AX58200/V0.10/11/22/19 |
Nº de peça semelhante - AX58200BI |
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Descrição semelhante - AX58200BI |
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