 |
Os motores de busca de Datasheet de Componentes eletrônicos |
|
|
Os motores de busca de Datasheet de Componentes eletrônicos |
|
AX58200BI Folha de dados(PDF) 136 Page - ASIX Electronics Corporation |
|
|
|||||||||||||||||||||||||||||
AX58200BI Folha de dados(HTML) 136 Page - ASIX Electronics Corporation |
|
|
136 / 180 page  136 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC 3.5.9 Digital to Analog Converter (DAC) Symbol Parameter Conditions Min Typ Max Units AV DD Analog supply voltage 1.8 - 3.6 V NR Resolution 12 bit V REF Reference supply voltage V REF ≤ AV DD 1.5 - AV DD V DNL Differential non-linearity error[*4] 12-bit mode - - ±2 LSB 10-bit mode - - ±0.5 LSB INL Integral non-linearity error[*4] 12-bit mode - - ±4 LSB 10-bit mode - - ±1 LSB OE Offset Error[*4] 12-bit mode DACOUT buffer ON - - ±6 LSB 12-bit mode DACOUT buffer OFF - - ±4 LSB 10-bit mode - - ±2 LSB GE Gain Error[*4] 12-bit mode DACOUT buffer ON - - ±5 LSB 12-bit mode DACOUT buffer OFF - - ±4 LSB 10-bit mode - - ±2 LSB AE Absolute Error[*4] 12-bit mode DACOUT buffer ON - - ±8 LSB 12-bit mode DACOUT buffer OFF - - ±4 LSB 10-bit mode - - ±2 LSB - Monotonic 10-bit guaranteed VO Output Voltage DACOUT buffer ON 0.2 AV DD - 0.2 V RLOAD Resistive load[*2] DACOUT buffer ON 7.5 - - kΩ Ro Output impedance[*4] DACOUT buffer OFF 10 12 kΩ CLOAD Capacitive load[*3] - - - 50 pF IAVDD Current consumption on AVDD supply[*4] AV DD = 3.6V, no load, lowest code (0x000) - - 180 A AV DD = 3.6V, no load, middle code (0x800) - - 420 I REF Current consumption on VREF supply[*4] VREF =3.6V, no load, middle code (0x800) - 150 240 A T S Settling Time Full scale: for a 12-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value +/-1 LSB, CLOAD ≤ 50pF, RLOAD ≥ 7.5kΩ - 5 6 μs Fs Update Rate Max. frequency for a correct DAC_OUT change from core i to i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 7.5kΩ - - 1 MSPS TWAKEUP Wake-up Time Wakeup time from OFF state. Input code between lowest and highest possible codes. DAC clock source = 1MHz - 9 15 μs PSRR Power Supply Rejection Ratio[*1] No RLOAD, CLOAD = 50pF - -60 -40 dB Note: 1. Guaranteed by design, not tested in production. 2. Resistive load between DACOUT and AVSS. 3. Capacitive load at DACOUT pin. 4. Guaranteed based on test during characterization. |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
