AM652X datasheet(274/299 Pages) TI1

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274

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

6.11.21 OSPI

The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI)

module which allows single, dual, quad or octal read and write access to external flash devices. This

module has a memory mapped register interface, which provides a direct memory interface for accessing

data from external flash devices, simplifying software requirements.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a

processor wishing to execute code directly from external flash memory), or in an indirect mode where the

module is set-up to silently perform some requested operation, signalling its completion via interrupts or

status registers. For indirect operations, data is transferred between system memory and external flash

memory via an internal SRAM which is loaded for writes and unloaded for reads by a device master at low

latency system speeds. Interrupts or status registers are used to identify the specific times at which this

SRAM should be accessed using user programmable configuration registers.

The OSPI modules have the following features:

•

Support for single, dual, quad (QSPI mode) or octal (on MCU_FSS0_OSPI0 only) I/O instructions.

•

Support dual Quad-SPI mode for fast boot applications.

•

Memory mapped ‘direct’ mode of operation for performing flash data transfers and executing code from

flash memory.

•

Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive

flash data transfers.

•

Local SRAM of configurable size to reduce advanced high-performance bus overhead and buffer flash

data during indirect transfers.

•

Set of software advanced peripheral bus accessible flash control registers to perform any flash

command, including data transfers up to 8-bytes at a time.

•

Additional addressable Memory Bank to accommodate more than 8-bytes at a time.

•

Supports any device clock frequency, including frequencies of:

–

166 MHz SDR or 200 MHz DDR (with DQS) for Octal-SPI devices

–

133 MHz SDR or 70 MHz DDR for Quad-SPI devices

•

Support for XIP (Execute in Place), sometimes referred to as continuous mode.

•

Support for DDR Mode and DTR protocol (including Octal DDR protocol with DQS for Octal-SPI

devices)

•

Programmable device sizes.

•

Programmable write protected regions to block system writes from taking effect.

•

Programmable delays between transactions.

•

Legacy mode allowing software direct access to low level transmit and receive FIFOs, bypassing the

higher layer processes.

•

An independent reference clock to decouple bus clock from SPI clock – allows slow system clocks.

•

Programmable baud rate generator to generate OSPI clocks.

•

Features included to improve high speed read data capture mechanism.

•

Option to use adapted clocks or DQS to further improve read data capturing.

•

Programmable interrupt generation.

•

Up to four external device selects - OSPI and QSPI devices can be mixed:

–

MCU_FSS0_OSPI0 has four chip-selects

–

MCU_FSS0_OSPI1 has two chip-selects.

•

Programmable data decoder, enables continuous addressing mode for each of connected devices and

auto-detection of boundaries between devices.

•

Support BOOT mode.

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