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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AM652X Folha de dados(PDF) 248 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 248 Page - Texas Instruments |
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248 / 299 page  248 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated • Power Management features – DMSC Control Module • Contains various control, configuration and status MMRs for power management functions. – Main Oscillator Control • Controls the main SOC oscillator power down. • Controls the POR-RC oscillator root clock gating to avoid high frequency clock propagation during the SOC DeepSleep and DeeperSleep . • Support for DMTIMER to continue counting and generate interrupt via SWAKEUP even during SOC oscillator power down mode. The 4 DMTIMER modules support SWAKEUP generation. – Memory power management • Power OFF of ROM during sleep modes. • Retention of RAM during sleep modes. – IO Power Management • Controls IO Isolation while going into Standby mode. • Controls IO Wakeup capability. – External signals for power control • Support for 64 Cortex-M3 controlled general purpose outputs. • Support for 64 general purpose inputs which can be used by Cortex-M3. • Support for 64 hardware controlled outputs. • Support for 64 hardware controlled inputs. • Security Control features – Security Manager module • Device security management • Device type control (GP, EMU, HS etc.). • Emulation control • JTAG control • Key Management – Firewall and Priv-ID manager • Dedicated VBUSP port for firewall emulation and security configuration. • Issues interrupt to Cortex-M3 upon exception detection. • Accessible by Cortex-M3 only as default setting. – Debug SS handshake protocol for challenge-response protocol • Communication channel between DebugSS and DMSC to carry-out challenge response protocol to open SoC level JTAG port. – AES engine with 128, 192 and 256-bits support • No data fetch engine, data pushed via host into AES registers. • Separate firewall control for two HIB. • Ability to select KEK as default key for AES operation. • DPA /EMA countermeasure DMSC module Not Supported features: • Cortex-M3 Memory Protection Unit (MPU) • ETM • No big-endian support. • No support for SWAKEUP/CLKSTOP_WAKEUP event generation from WW-RTI. For more information, see section Device Management and Security Controller (DMSC) in chapter Device Configuration of the device TRM. |
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