AM652X datasheet(246/299 Pages) TI1

246 / 299 page

246

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

The following PRU_ICSSG features are not supported:

•

Only 4 of the IEP0 (and none of the IEP1) Ethernet Digital Data Input/Output's of each ICSS_G are

pinned out

•

UART Modem interface is not supported

•

The following features are not supported only for PRU_ICSSG0 and PRU_ICSSG1

–

12 Enhanced General-Purpose Inputs (pr<0/1>_pru0_r31_in[31:20]) are not pinned out

–

12 Enhanced General-Purpose Outputs (pr<0/1>_pru0_r31_out[31:20]) are not pinned out

–

SGMII mode is not supported on PRU_ICSSG0 and PRU_ICSSG1

•

The following features are not supported only for PRU_ICSSG2:

–

14 Enhanced General-Purpose Inputs (pr<2>_pru0_r31_in[31:18]) are not pinned out

–

14 Enhanced General-Purpose Outputs (pr<2>_pru0_r31_out[31:18]) are not pinned out

For

information,

see

section

Programmable

Real-Time

Unit

Subsystem

and

Industrial

Communication Subsystem - Gigabit (PRU_ICSSG) in chapter Processors and Accelerators of the device

TRM.

6.7

DMSC

This section describes the Device Management and Security Controller (DMSC) module in the device.

NOTE

DMSC controls the boot sequence, power management and security of the device, hence

does not fall under specific industry standards.

The device supports one DMSC module - WKUP_DMSC0, located in WKUP domain

A dedicated subsystem for device management and security functions. The DMSC is located in the

WKUPSS. With the factory-sealed firmware, DMSC performs:

•

Device management

•

On-chip power management

•

Secure boot gate-keeping

•

Runtime security gate-keeping

•

Power feature /Wake-up control

DMSC module supports the following features:

•

Arm Cortex-M3 based subsystem

–

Boot sequence

–

Device management

–

Power management

–

Security control

•

Arm Cortex-M3 RISC Processor (Single core)

–

Armv7-M architecture profile.

–

Support for NVIC (Nested Vectored Interrupt Controller) to achieve low interrupt latency

–

Ability to execute code from internal memory (via I-code/D-code) or external memories

•

Read-only Memory (ROM) to allow boot sequence, authentication and provide security service

–

160KB Size (4-bytes words).

–

Accessible to only Cortex-M3.

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