SPEAR600 datasheet(22/97 Pages) STMICROELECTRONICS

22 / 97 page

Architecture overview

SPEAr600

22/97

Doc ID 16259 Rev 3

Two different modes of operation are available:

●

Auto-reload mode, an interrupt source is activated, the counter is automatically cleared

and then it restarts incrementing.

●

Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT

is disabled.

2.22

Watchdog timer

The ARM watchdog module consists of a 32-bit down counter with a programmable time-out

interval that has the capability to generate an interrupt and a reset signal on timing out. The

watchdog module is intended to be used to apply a reset to a system in the event of a

software failure.

2.23

RTC oscillator

The RTC provides a 1-second resolution clock. This keeps time when the system is inactive

and can be used to wake the system up when a programmed alarm time is reached. It has a

clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a

secured time update.

Main features:

●

Time-of-day clock in 24 hour mode

●

Calendar

●

Alarm capability

●

Isolation mode, allowing RTC to work even if power is not supplied to the rest of the

device.

2.24

Reconfigurable array subsystem connectivity (RAS)

The Reconfigurable Logic Array consists of an embedded macro where it is possible to

implement a custom project by mapping up to 600k equivalent standard cells. The user can

design custom logic and special function using various features offered by the

Reconfigurable Logic Array and by the SPEAr600 system listed here below.

●

4 AHB bus master interfaces

●

5 AHB bus slave interfaces

●

Dedicated interface with CPU1 to customize the Tightly Couple Memory

●

Dedicated interface with CPU1 to customize the Coprocessor

●

Dedicated interface with CPU2 to customize the Tightly Coupled Memory

●

Interfaces towards a dedicated 130 kB Memory Array Subsystem provided of functional

BIST driven by SoC via software and divided in the following ST memory cuts:

–

3 single port memory cuts (48 words x 128 bits)

–

4 single port memory cuts (2048 words x 32 bits)

–

8 single port memory cuts (1024 words x 32 bits)

–

16 single port memory cuts (512 words x 32 bits)

–

8 dual port memory cuts (512 words x 32 bits)

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