SPEAR600 datasheet(86/97 Pages) STMICROELECTRONICS

86 / 97 page

Timing characteristics

SPEAr600

86/97

Doc ID 16259 Rev 3

6.8

SSP timing characteristics

The device SPEAr600 contains 3 SSP modules. The Low Speed Connectivity Subsystem

contains SSP1 and SSP2, the Application Subsystem contains SSP3. These 3 identical

modules provide a programmable length shift register which allows serial communication

with other SSP devices through a 3 or 4 wire interface (SSP_SCLK, SSP_MISO,

SSP_MOSI and SSP_SS). The SSP module supports the following features:

●

Master/Slave mode operations

●

Programmable clock bit rate and prescaler

●

Programmable choice of interface operation: SPI, Microwire or TI synchronous serial

Programmable data frame size from 5 to 16 bits

●

Separate transmit and receive FIFO, 16 bits wide, 8 locations deep

The features of the Motorola SPI-compatible interface are:

●

Full duplex, four-wire synchronous transfers (SSP_SCLK, SSP_MISO, SSP_MOSI and

SSP_SS)

●

Programmable Clock Polarity (CPOL) and Clock Phase (CPHA)

The following Tables show the Timing Requirements of the SPI four-wire synchronous

transfer for the 3 SSP modules present in the Spear600 configured in master mode

(indicated in the tables as SPI1, SPI2 and SPI3). Both the Timings on MISO (master input

slave output) pad and MOSI (master output slave input) pad are provided.

T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a

configurable divider.

Figure 43.

SSP_CLK timing

Table 56.

Timing requirements for SSP (all modes)

No.

parameters

value

unit

Tc(CLK)

Cycle time, SSP_SCLK

24 (min)

Tw(CLKH)

Pulse duration, SSP_SCLK high

.49T - .51T

Tw(CLKL)

Pulse duration, SSP_SCLK low

.51T - .49T

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