SPEAR600 datasheet(61/97 Pages) STMICROELECTRONICS

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SPEAr600

Timing characteristics

Doc ID 16259 Rev 3

61/97

Table 32 shows the internal chip timing without the contribution of the pads.

These values are obtained considering the nominal setting of DLL at T/4 period, in fact, the

DDR memory launches data (DQ) and data strobe (DQS) aligned. Internally the DQS is

delayed by T/4 (DLL) to guarantee correct data capture.

The waveforms in Figure 4 refers to the pad or memory side: so the data move around the

edges of DQS signals. In this case, we consider the maximum values for t4 and t5 to obtain

the minimum data valid window. For correct data capture (at the controller side) the last

arrival time of the data (last variation) must precede the first arrival of the data strobe:

t4MAX = DQS (delay)MIN - DQ (delay)MAX = (t1MIN + t2MIN + T/4 ±one DLL element

(a) ) -

t3MAX

t5 can be expressed in a similar way:

t5MAX = DQ (delay)MIN - DQS (delay)MAX = (T/2 + t3MIN) - (t1MAX + t2MAX + T/4 ± one DLL

element(a)) = T/4 + t3MIN - t1MAX - t2MAX ± one DLL element

(a)

Note:

DQS (delay) is the combination of delays experienced by the DQS (data strobe) signal, DQ

(delay) is the combination of delays experienced by the DQ (data) signal (both until the

capture is performed by the controller).

DQS (delay) depends on t1 and t2 while DQ (delay) depends on t3.

6.1.2

DDR2 write cycle timings

Figure 6.

DDR2 write cycle waveforms

5 ns

200 MHz

1.31 ns

842 ps

6 ns

166 MHz

1.56 ns

1.10 ns

7.5 ns

133 MHz

1.93 ns

1.47 ns

The value “one DLL element” stands for the DLL accuracy, so we put ± one DLL element in the formulas. One

DLL element = 15 ps in best case and 85 ps in worst case.

Table 32.

DDR2 read cycle timings without pad delay (continued)

Period (T)

Frequency

t4MAX

t5MAX

DQS

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