SPC564A80B4 datasheet(26/157 Pages) STMICROELECTRONICS

26 / 157 page

Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

26/157

Doc ID 15399 Rev 9

1.5.17

FlexRay

The SPC564A80 includes one dual-channel FlexRay module that implements the FlexRay

Communications System Protocol Specification, Version 2.1 Rev A. Features include:

●

Single channel support

●

FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported

●

128 message buffers, each configurable as:

–

Receive message buffer

–

Single buffered transmit message buffer

–

Double buffered transmit message buffer (combines two single buffered message

buffer)

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2 independent receive FIFOs

–

1 receive FIFO per channel

–

Up to 255 entries for each FIFO

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ECC support

1.5.18

System timers

The system timers include two distinct types of system timer:

●

Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)

●

Operating system task monitors using the System Timer Module (STM)

Periodic interrupt timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts

and periodic triggers. The PIT has no external input or output pins and is intended to provide

system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues.

Of the five channels in the PIT, four are clocked by the system clock and one is clocked by

the crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is

used to wake up the device from low power stop mode.

The following features are implemented in the PIT:

●

5 independent timer channels

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Each channel includes 32-bit wide down counter with automatic reload

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4 channels clocked from system clock

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1 channel clocked from crystal clock (wake-up timer)

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Wake-up timer remains active when System STOP mode is entered; used to restart

system clock after predefined time-out period

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Each channel optionally able to generate an interrupt request or a trigger event (to

trigger eQADC queues) when timer reaches zero

System timer module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as

defined by AUTOSAR(b). It consists of a single 32-bit counter, clocked by the system clock,

AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

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