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STTS2004 Folha de dados(PDF) 34 Page - STMicroelectronics |
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STTS2004 Folha de dados(HTML) 34 Page - STMicroelectronics |
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34 / 58 page ![]() SPD EEPROM operation STTS2004 34/58 DocID024229 Rev 3 code is received, the device only responds if the slave address is the same as the value on the slave address (A0, A1, A2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. The operating modes are detailed in Table 24. 5.4 Setting the write protection There are four independent memory blocks, and each block may be independently protected. The memory blocks are: Block 0 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 0 Block 1 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 0 Block 2 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 1 Block 3 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 1 The device has three software commands for setting, clearing, or interrogating the write protection status. SWPn: Set Write Protection for block n CWP: Clear Write Protection for all blocks RPSn: Read Protection status for block n The level of write protection (set or cleared), that has been defined using these instructions, remains defined even after a power cycle. The DTICs of the SWP, CWP, and RPS instructions are defined in Table 2. 5.4.1 Set and clear the write protection (SWPn and CWP) If the software write protection has been set with the SWPn instruction, it may be cleared again with a CWP instruction. SWPn acts on a single block as specified in the SWPn command, but CWP clears the write protection for all blocks. When decoded, SWPn and CWPn trigger a write cycle lasting tW (see Table 33). The DTICs of the SWP and CWP instructions are defined in Table 2. Table 24. Operating modes Mode RW bit Bytes Initial sequence Current address read 1 1 START, device select, RW = 1 Random address read 0 1 START, device select, RW = 0, address 1 reSTART, device select, RW = 1 Sequential read 1 1 Similar to current or random address read Byte write 0 1 START, device select, RW = 0 Page write 0 16 START, device select, RW = 0 TS write 0 2 START, device select, R/W = 0, pointer data, stop TS read 1 2 START, device select, R/W = 1, pointer data, stop |
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