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LT1737

1737f

MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS

The LT1737 is a current mode controller. It uses the VC

node voltage as an input to a current comparator that turns

off the output switch on a cycle-by-cycle basis as this peak

current is reached. The internal clamp on the VC node,

nominally 2.5V, then acts as an output switch peak current

limit.

This 2.5V at the VC pin corresponds to a value of 250mV

at the ISENSE pin, when the (ON) switch duty cycle is less

than 40%. For a duty cycle above 40%, the internal slope

compensation mechanism lowers the effective ISENSE

voltage limit. For example, at a duty cycle of 80%, the

nominal ISENSE voltage limit is 220mV. This action be-

comes the switch current limit specification. Maximum

available output power is then determined by the switch

current limit, which is somewhat duty cycle dependent

due to internal slope compensation action.

Overcurrent conditions are handled by the same mecha-

nism. The output switch turns on, the peak current is

quickly reached and the switch is turned off. Because the

output switch is only on for a small fraction of the available

period, power dissipation is controlled.

Loss of current limit is possible under certain conditions.

Remember that the LT1737 normally exhibits a minimum

switch on time, irrespective of current trip point. If the duty

cycle exhibited by this minimum on time is greater than the

ratio of secondary winding voltage (referred-to-primary)

divided by input voltage, then peak current will not be

controlled at the nominal value, and will cycle-by-cycle

ratchet up to some higher level. Expressed mathemati-

cally, the requirement to maintain short-circuit control is:

SEC

•

()

where

tON = output switch minimum on time

f = switching frequency

ISC = short-circuit output current

VF = output diode forward voltage at ISC

RSEC = resistance of transformer secondary

VIN = input voltage

NSP = secondary-to-primary turns ratio (NSEC/NPRI)

Trouble is typically only encountered in applications with

a relatively high product of input voltage times secondary-

to-primary turns ratio and/or a relatively long minimum

switch on time. (Additionally, several real world effects such

as transformer leakage inductance, AC winding losses, and

output switch voltage drop combine to make this simple

theoretical calculation a conservative estimate.)

THERMAL CONSIDERATIONS

Care should be taken to ensure that the worst-case input

voltage condition does not cause excessive die tempera-

tures. The 16-lead SO package is rated at 100

°C/W, and

the 16-lead GN at 110

°C/W.

Average supply current is simply the sum of quiescent

current given in the specifications section plus gate drive

current. Gate drive current can be computed as:

IG = f • QG where

QG = total gate charge

f = switching frequency

(Note: Total gate charge is more complicated than CGS • VG

as it is frequently dominated by Miller effect of the CGD.

Furthermore, both capacitances are nonlinear in practice.

Fortunately, most MOSFET data sheets provide figures

and graphs which yield the total gate charge directly per

operating conditions.) Nearly all gate drive power is dissi-

pated in the IC, except for a small amount in the external

gate series resistor, so total IC dissipation may be com-

puted as:

PD(TOTAL) = VCC (IQ + • f • QG ), where

IQ = quiescent current (from specifications)

QG = total gate charge

f = switching frequency

VCC = LT1737 supply voltage

SWITCH NODE CONSIDERATIONS

For maximum efficiency, gate drive rise and fall times are

made as short as practical. To prevent radiation and high

frequency resonance problems, proper layout of the

components connected to the IC is essential, especially

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