LT1737IGN datasheet(18/28 Pages) LINER

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LT1737

1737f

Output Impedance Error

An additional error source is caused by transformer sec-

ondary current flow through the real life nonzero imped-

ances of the output rectifier, transformer secondary and

output capacitor. Because the secondary current only

flows during the off portion of the duty cycle, the effective

output impedance equals the “DC” lumped secondary

impedance times the inverse of the off duty cycle. If the

output load current remains relatively constant, or, in less

critical applications, the error may be judged acceptable

and the feedback resistor divider ratio adjusted for nomi-

nal expected error. In more demanding applications, out-

put impedance error may be minimized by the use of the

load compensation function (see Load Compensation).

MINIMUM LOAD CONSIDERATIONS

The LT1737 generally provides better low load perfor-

mance than previous generation switcher/controllers uti-

lizing indirect output voltage sensing techniques.

Specifically, it contains circuitry to detect flyback pulse

“collapse,” thereby supporting operation well into discon-

tinuous mode. Nevertheless, there still remain constraints

to ultimate low load operation. These relate to the mini-

mum switch on time and the minimum enable time.

Discontinuous mode operation will be assumed in the

following theoretical derivations.

As outlined in the Operation section, the LT1737 utilizes a

minimum output switch on time, tON. This value can be

combined with expected VIN and switching frequency to

yield an expression for minimum delivered power.

Minimum Power

PRI

OUT

= 





()

•

This expression then yields a minimum output current

constraint:

OUT MIN

PRI

OUT

()

•

= 





()

where

f = switching frequency

LPRI = transformer primary side inductance

VIN = input voltage

VOUT = output voltage

tON = output switch minimum on time

An additional constraint has to do with the minimum

enable time. The LT1737 derives its output voltage infor-

mation from the flyback pulse. If the internal minimum

enable time pulse extends beyond the flyback pulse, loss

of regulation will occur. The onset of this condition can be

determined by setting the width of the flyback pulse equal

to the sum of the flyback enable delay, tED, plus the

minimum enable time, tEN. Minimum power delivered to

the load is then:

Minimum Power

SEC

OUT

= 







()

[]

•

Which yields a minimum output constraint:

OUT MIN

OUT

SEC

()

•

= 







()

where

f = switching frequency

LSEC = transformer secondary side inductance

VOUT = output voltage

tED = enable delay time

tEN = minimum enable time

Note that generally, depending on the particulars of input

and output voltages and transformer inductance, one of

the above constraints will prove more restrictive. In other

words, the minimum load current in a particular applica-

tion will be either “output switch minimum on time”

constrained, or “minimum flyback pulse time” constrained.

(A final note—LPRI and LSEC refer to transformer induc-

tance as seen from the primary or secondary side respec-

tively. This general treatment allows these expressions to

be used when the transformer turns ratio is nonunity.)

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