A25GFM080QL datasheet(29/58 Pages) AMICC

29 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Quad Input Fast Program (QIFP)

The Quad Input Fast Program (QIFP) instruction is very

similar to the Page Program (PP) instruction, except that the

data are entered on four pins (IO3, IO2, IO1, IO0) instead of

only one. Inputting the data on four pins instead of one

quadruples the data transfer bandwidth compared to the

Page Program (PP) instruction. To use Quad Input Fast

Program the Quad Enable bit (QE) of Status Register-2 must

be set.

The Quad Input Fast Program (QIFP) instruction is entered

by driving Chip Select ( S ) Low, followed by the instruction

code, three address bytes and at least one data byte on Data

Input Output (IO3, IO2, IO1, IO0).

If the 8 least significant address bits (A7-A0) are not all zero,

all transmitted data that goes beyond the end of the current

page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0)

are all zero). Chip Select ( S ) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 18.

If more than 256 bytes are sent to the device, previously

latched data are discarded and the last 256 data bytes are

guaranteed to be programmed correctly within the same

page. If less than 256 data bytes are sent to device, they are

correctly programmed at the requested addresses without

having any effects on the other bytes in the same page.

For optimized timings, it is recommended to use the Quad

Input Fast Program (QIFP) instruction to program all

consecutive targeted bytes in a single sequence rather to

using several Quad Input Fast Program (QIFP) sequences

each containing only a few bytes.

Chip Select ( S ) must be driven High after the eighth bit of

the last data byte has been latched in, otherwise the Quad

Input Fast Program (QIFP) instruction is not executed.

As soon as Chip Select ( S ) is driven High, the self-timed

Page Program cycle (whose duration is tPP) is initiated. While

the Quad Input Fast Program (QIFP) cycle is in progress, the

Status Register may be read to check the value of the Write

In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Page Program cycle, and 0 when it is

completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

A Quad Input Fast Program (QIFP) instruction applied to a

page that is protected by the Block Protect (CMP, SEC, TB,

BP2, BP1, BP0) bits (see Table 1) is not executed.

Figure 18. Quad Input Fast Program (QIFP) instruction sequence

IO0

Instruction (32h)

MSB

810

0 1 234 5 6 7

24-Bit Address

28 29 30 31 32 33 34 35 36 37 38 39

23 22 21

3 21 0 4 0 40 40 4 0

53 54

IO0

Byte 1 Byte 2 Byte 3 Byte 4

5 1 51 51 51

6 2 62 62 62

7 3 73 73 73

MSB

IO1

IO2

IO3

5 1 51 51 5

5 1 51 51 5 1

6 2 62 62 6

6 2 62 62 6 2

7 3 73 73 7

7 3 73 73 7 3

4 0 40 40 4

4 0 40 40 4 0

Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10Byte 11 Byte 12 Byte 253 Byte 254Byte 255 Byte 256

IO1

IO2

IO3

Note: Address bits A23 to A20 are Don’t Care, for A25LQ080

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