A25GFM080QL datasheet(14/58 Pages) AMICC

14 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 3.) sets the

Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every

Page Program (PP), Dual Input Fast Program (DIFP), Quad

Input Fast Program (QIFP), Program OTP (POTP), Sector

Erase (SE), Block Erase (BE), and Chip Erase (CE) and Write

Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving

Chip Select (

S ) Low, sending the instruction code, and then

driving Chip Select (

S ) High.

Figure 3. Write Enable (WREN) Instruction Sequence

High Impedance

Instruction (06h)

0 1 23 45 6 7

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 4.) resets the

Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip

Select ( S ) Low, sending the instruction code, and then driving

Chip The Write Enable Latch (WEL) bit is reset under the

following conditions:

﹣ Power-up

﹣

Write Disable (WRDI) instruction completion

﹣

Write Status Register (WRSR) instruction completion

﹣

Page Program (PP) instruction completion

﹣

Dual Input Fast Program (DIFP) instruction completion

﹣

Quad Input Fast Program (QIFP) instruction completion

﹣

Program OTP (POTP) in

struction completion

﹣

Sector Erase (SE) instruction completion

﹣

Block Erase (BE) instruction completion

﹣

Chip Erase (CE) instruction completion

Figure 4. Write Disable (WRDI) Instruction Sequence

High Impedance

Instruction (04h)

0 1 23 45 6 7

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