UCD3138128APFC datasheet(29/83 Pages) TI1

29 / 83 page

UCD3138128A

www.ti.com

SLUSC99 – JULY 2016

Product Folder Links: UCD3138128A

Submit Documentation Feedback

9.3.2.1.4

High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM

edges, the UCD3138xA DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the

resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz. The high

resolution section of DPWM can be enabled or disabled, and the resolution can be defined in several steps

between 4 ns to 250 ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN and HIRES_SCALE

inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details.

9.3.2.1.5

Oversampling

The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error

voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register

value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the

time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting

triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X.

9.3.2.1.6

DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the

period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt

service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence

synchronization. Table 4 outlines the divide ratios that can be programmed.

9.3.2.1.7

DPWM Interrupt Scaling/Range

Table 4. DPWM Interrupt Divide Ratio

Interrupt Divide

Setting

Interrupt Divide

Count

Interrupt Divide

Count (hex)

Switching Period

Frames (Assume 1-MHz

Loop)

Number of 32-MHz

Processor Cycles

128

256

512

1024

1536

2048

2560

3072

127

128

4096

159

160

5120

191

192

6144

223

224

7168

255

256

8192

9.3.2.1.8

Synchronous Rectifier Dead Time Optimization Peripheral

The UCD3138xA has an advanced dead time control interface where it can accept UCD7138 output signals and

optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-performance driver

for secondary-side synchronous rectification (SR) with body diode conduction sensing. The device is suitable for

high power high efficiency isolated converter applications where dead-time optimization is desired. The UCD7138

gate driver is a companion device to UCD3138xA highly integrated digital controller for isolated power.

UCD3138128APFC Folha de dados(PDF) 29 Page - Texas Instruments

UCD3138128APFC Folha de dados(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Folha de dados Download

Ligação URL