UCD3138128APFC datasheet(28/83 Pages) TI1

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Start of Period

Period Counter

Start of Period

Period

Sample Trigger 1

DPWM Output A

Cycle Adjust A (High Resolution)

Event 2 (High Resolution)

Event 1

Event 3 (High Resolution)

Cycle Adjust B (High Resolution)

Event 4 (High Resolution)

DPWM Output B

Blanking A Begin

Blanking A End

Blanking B Begin

Blanking B End

Phase Trigger

Sample Trigger 2

To Other

Modules

To Other

Modules

UCD3138128A

SLUSC99 – JULY 2016

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Figure 13 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own

registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are

used to blank fault measurements during noisy events, such as FET turn on and turn off.

Events which change with DPWM mode:

•

DPWM A Rising Edge = Event 1

•

DPWM A Falling Edge = Event 2 + Cycle Adjust A

•

DPWM B Rising Edge = Event 3

•

DPWM B Falling Edge = Event 4 + Cycle Adjust B

•

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

•

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B

•

Begin, Blanking B End

Figure 13. Multi Mode Open Loop

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