CC1150-RTY1 datasheet(14/67 Pages) TI1

14 / 67 page

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

Hi-Z

CC1150

SWRS037B – JANUARY 2006 – REVISED MARCH 2015

www.ti.com

Figure 5-4. Configuration Registers Write and Read Operations

Table 5-1. SPI Interface Timing Requirements

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SCLK frequency

—

100 ns delay inserted between address byte and data byte (single access), or

between address and data, and between each data byte (burst access).

SCLK frequency, single access

fSCLK

MHz

No delay between address and data byte

SCLK frequency, burst access

6.5

No delay between address and data byte, or between data bytes

tsp,pd

CSn low to positive edge on SCLK, in power-down mode

150

—

µs

tsp

CSn low to positive edge on SCLK, in active mode

—

tch

Clock high

—

tcl

Clock low

—

trise

Clock rise time

—

tfall

Clock fall time

—

Setup data (negative SCLK edge) to positive edge on

Single access

—

SCLK

tsd

(tsd applies between address and data bytes, and

Burst access

—

between data bytes)

thd

Hold data after positive edge on SCLK

—

tns

Negative edge on SCLK to CSn high

—

NOTE

The minimum tsp,pd figure in Table 5-1 can be used in cases where the user does not read

the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from

power-down depends on the start-up time of the crystal being used. The 150

μs in Table 5-1

is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.

5.5.1

Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is

sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The

first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The

CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power

to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and

channel configuration should only be updated when the chip is in this state. The TX state will be active

when the chip is transmitting.

Detailed Description

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