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COP8CSDR9KMT7 Folha de dados(PDF) 63 Page - National Semiconductor (TI) |
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COP8CSDR9KMT7 Folha de dados(HTML) 63 Page - National Semiconductor (TI) |
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63 / 80 page ![]() 18.0 Memory Map (Continued) Address Contents S/ADD REG xxE7 Timer T1 Autoload Register T1RB Upper Byte xxE8 ICNTRL Register xxE9 MICROWIRE/PLUS Shift Register xxEA Timer T1 Lower Byte xxEB Timer T1 Upper Byte xxEC Timer T1 Autoload Register T1RA Lower Byte xxED Timer T1 Autoload Register T1RA Upper Byte xxEE CNTRL Control Register xxEF PSW Register xxF0 to FB On-Chip RAM Mapped as Registers xxFC X Register Address Contents S/ADD REG xxFD SP Register xxFE B Register xxFF S Register 0100 to 017F On-Chip 128 RAM Bytes 0200 to 027F On-Chip 128 RAM Bytes 0300 to 037F On-Chip 128 RAM Bytes 0400 to 047F On-Chip 128 RAM Bytes 0500 to 057F On-Chip 128 RAM Bytes 0600 to 067F On-Chip 128 RAM Bytes 0700 to 077F On-Chip 128 RAM Bytes Note: Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading unused memory locations 0080H–0093H (Segment 0) will return undefined data. Reading memory locations from other Seg- ments (i.e., Segment 8, Segment 9, … etc.) will return undefined data. www.national.com 63 |
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