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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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COP8CSDR9KMT7 Folha de dados(PDF) 62 Page - National Semiconductor (TI) |
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COP8CSDR9KMT7 Folha de dados(HTML) 62 Page - National Semiconductor (TI) |
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62 / 80 page  18.0 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As All Ones) xx80 to xx90 Unused RAM Address Space (Reads Undefined Data) xx90 Port E Data Register xx91 Port E Configuration Register xx92 Port E Input Pins (Read Only) xx93 Reserved for Port E xx94 Port F Data Register xx95 Port F Configuration Register xx96 Port F Input Pins (Read Only) xx97 Reserved for Port F xx98 to xx9F Reserved xxA0 Port A Data Register xxA1 Port A Configuration Register xxA2 Port A Input Pins (Read Only) xxA3 Reserved for Port A xxA4 Port B Data Register xxA5 Port B Configuration Register xxA6 Port B Input Pins (Read Only) xxA7 Reserved for Port B xxA8 ISP Address Register Low Byte (ISPADLO) xxA9 ISP Address Register High Byte (ISPADHI) xxAA ISP Read Data Register (ISPRD) xxAB ISP Write Data Register (ISPWR) xxAC Reserved xxAD Reserved xxAE Reserved xxAF High Speed Timers Control Register (HSTCR) xxB0 Timer T3 Lower Byte xxB1 Timer T3 Upper Byte xxB2 Timer T3 Autoload Register T3RA Lower Byte xxB3 Timer T3 Autoload Register T3RA Upper Byte xxB4 Timer T3 Autoload Register T3RB Lower Byte xxB5 Timer T3 Autoload Register T3RB Upper Byte xxB6 Timer T3 Control Register xxB7 Reserved xxB8 USART Transmit Buffer (TBUF) xxB9 USART Receive Buffer (RBUF) Address Contents S/ADD REG xxBA USART Control and Status Register (ENU) xxBB USART Receive Control and Status Register (ENUR) xxBC USART Interrupt and Clock Source Register (ENUI) xxBD USART Baud Register (BAUD) xxBE USART Prescale Select Register (PSR) xxBF Reserved for USART xxC0 Timer T2 Lower Byte xxC1 Timer T2 Upper Byte xxC2 Timer T2 Autoload Register T2RA Lower Byte xxC3 Timer T2 Autoload Register T2RA Upper Byte xxC4 Timer T2 Autoload Register T2RB Lower Byte xxC5 Timer T2 Autoload Register T2RB Upper Byte xxC6 Timer T2 Control Register xxC7 WATCHDOG Service Register (Reg:WDSVR) xxC8 MIWU Edge Select Register (Reg:WKEDG) xxC9 MIWU Enable Register (Reg:WKEN) xxCA MIWU Pending Register (Reg:WKPND) xxCB to xxCE Reserved xxCF Idle Timer Control Register (ITMR) xxD0 Port L Data Register xxD1 Port L Configuration Register xxD2 Port L Input Pins (Read Only) xxD3 Reserved for Port L xxD4 Port G Data Register xxD5 Port G Configuration Register xxD6 Port G Input Pins (Read Only) xxD7 Reserved xxD8 Port C Data Register xxD9 Port C Configuration Register xxDA Port C Input Pins (Read Only) xxDB Reserved for Port C xxDC Port D xxDD to xxDF Reserved for Port D xxE0 Reserved xxE1 Flash Memory Write Timing Register (PGMTIM) xxE2 ISP Key Register (ISPKEY) xxE3 to xxE5 Reserved xxE6 Timer T1 Autoload Register T1RB Lower Byte www.national.com 62 |
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