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COP8CSDR9KMT7 Folha de dados(PDF) 45 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças COP8CSDR9KMT7
Descrição Electrónicos  8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
PDF  80 Pages
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP8CSDR9KMT7 Folha de dados(HTML) 45 Page - National Semiconductor (TI)

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14.0 USART (Continued)
14.1 USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
14.2 DESCRIPTION OF USART REGISTER BITS
ENU — USART CONTROL AND STATUS REGISTER (Ad-
dress at 0BA)
PEN
PSEL1 XBIT9/
CHL1
CHL0
ERR
RBFL
TBMT
PSEL0
Bit 7
Bit 0
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
PEN = 0
Parity disabled.
PEN = 1
Parity enabled.
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL1 = 1
Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0
Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL1 = 1
Space(0) (if Parity enabled)
XBIT9/PSEL0: Programs the ninth bit for transmission when
the USART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity. Read/Write, cleared on reset.
CHL1, CHL0: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
10138925
FIGURE 22. USART Block Diagram
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