COP8CDR9KMT7 datasheet(67/84 Pages) NSC

67 / 84 page

19.0 Memory Map (Continued)

Address

Contents

S/ADD REG

xxB8

USART Transmit Buffer (TBUF)

xxB9

USART Receive Buffer (RBUF)

xxBA

USART Control and Status Register

(ENU)

xxBB

USART Receive Control and Status

xxBC

USART Interrupt and Clock Source

xxBD

USART Baud Register (BAUD)

xxBE

USART Prescale Select Register (PSR)

xxBF

Reserved for USART

xxC0

Timer T2 Lower Byte

xxC1

Timer T2 Upper Byte

xxC2

Timer T2 Autoload Register T2RA Lower

Byte

xxC3

Timer T2 Autoload Register T2RA Upper

Byte

xxC4

Timer T2 Autoload Register T2RB Lower

Byte

xxC5

Timer T2 Autoload Register T2RB Upper

Byte

xxC6

Timer T2 Control Register

xxC7

WATCHDOG Service Register

(Reg:WDSVR)

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

xxC9

MIWU Enable Register (Reg:WKEN)

xxCA

MIWU Pending Register (Reg:WKPND)

xxCB

A/D Converter Control Register (ENAD)

xxCC

A/D Converter Result Register High Byte

(ADRSTH)

xxCD

A/D Converter Result Register Low Byte

(ADRSTL)

xxCE

Reserved

xxCF

Idle Timer Control Register (ITMR)

xxD0

Port L Data Register

xxD1

Port L Configuration Register

xxD2

Port L Input Pins (Read Only)

xxD3

Reserved for Port L

xxD4

Port G Data Register

xxD5

Port G Configuration Register

xxD6

Port G Input Pins (Read Only)

xxD7

Reserved

xxD8

Port C Data Register

xxD9

Port C Configuration Register

xxDA

Port C Input Pins (Read Only)

xxDB

Reserved for Port C

xxDC

Port D

xxDD to xxDF

Reserved for Port D

Address

Contents

S/ADD REG

xxE0

Reserved

xxE1

Flash Memory Write Timing Register

(PGMTIM)

xxE2

ISP Key Register (ISPKEY)

xxE3 to xxE5

Reserved

xxE6

Timer T1 Autoload Register T1RB Lower

Byte

xxE7

Timer T1 Autoload Register T1RB Upper

Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift Register

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

xxEC

Timer T1 Autoload Register T1RA Lower

Byte

xxED

Timer T1 Autoload Register T1RA Upper

Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to FB

On-Chip RAM Mapped as Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

S Register

0100 to 017F

On-Chip 128 RAM Bytes

0200 to 027F

On-Chip 128 RAM Bytes

0300 to 037F

On-Chip 128 RAM Bytes

0400 to 0047F On-Chip 128 RAM Bytes

0500 to 057F

On-Chip 128 RAM Bytes

0600 to 067F

On-Chip 128 RAM Bytes

0700 to 077F

On-Chip 128 RAM Bytes

Note: Reading memory locations 0070H–007FH (Segment 0) will return all

ones. Reading unused memory locations 0080H–0093H (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 8, Segment 9, … etc.) will return undefined data.

20.0 Instruction Set

20.1 INTRODUCTION

This section defines the instruction set of the COP8 Family

members. It contains information about the instruction set

features, addressing modes and types.

20.2 INSTRUCTION FEATURES

The strength of the instruction set is based on the following

features:

•

Mostly single-byte opcode instructions minimize program

size.

•

One instruction cycle for the majority of single-byte in-

structions to minimize program execution time.

•

Many single-byte, multiple function instructions such as

DRSZ.

•

Three memory mapped pointers: two for register indirect

addressing, and one for the software stack.

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