COP8CDR9KMT7 datasheet(66/84 Pages) NSC

66 / 84 page

18.0 MICROWIRE/PLUS (Continued)

19.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

S/ADD REG

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads As

All Ones)

xx80 to xx90

Unused RAM Address Space (Reads

Undefined Data)

xx90

Port E Data Register

xx91

Port E Configuration Register

xx92

Port E Input Pins (Read Only)

xx93

Reserved for Port E

xx94

Port F Data Register

xx95

Port F Configuration Register

xx96

Port F Input Pins (Read Only)

xx97

Reserved for Port F

xx98 to xx9F

Reserved

xxA0

Port A Data Register

xxA1

Port A Configuration Register

xxA2

Port A Input Pins (Read Only)

xxA3

Reserved for Port A

xxA4

Port B Data Register

xxA5

Port B Configuration Register

xxA6

Port B Input Pins (Read Only)

Address

Contents

S/ADD REG

xxA7

Reserved for Port B

xxA8

ISP Address Register Low Byte

(ISPADLO)

xxA9

ISP Address Register High Byte

(ISPADHI)

xxAA

ISP Read Data Register (ISPRD)

xxAB

ISP Write Data Register (ISPWR)

xxAC

Reserved

xxAD

Reserved

xxAE

Reserved

xxAF

High Speed Timers Control Register

(HSTCR)

xxB0

Timer T3 Lower Byte

xxB1

Timer T3 Upper Byte

xxB2

Timer T3 Autoload Register T3RA Lower

Byte

xxB3

Timer T3 Autoload Register T3RA Upper

Byte

xxB4

Timer T3 Autoload Register T3RB Lower

Byte

xxB5

Timer T3 Autoload Register T3RB Upper

Byte

xxB6

Timer T3 Control Register

xxB7

Reserved

10137438

FIGURE 35. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High

10137439

FIGURE 36. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High

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