SPEAR320S-2 datasheet(15/113 Pages) STMICROELECTRONICS

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SPEAr320S

Device functions

Doc ID 022508 Rev 2

15/113

2.6

External memory interface (EMI)

SPEAr320S integrates an additional external memory interface that can be used to manage

external parallel NOR Flash memories as well as FPGA devices. This interface is available

only when Mode 3 (expanded automation mode) chip configuration is selected by software.

Main features:

●

24-bit address bus

●

16-bit data bus

●

4 chip select signals

●

Support for single asynchronous transfers

●

Support for peripherals using Byte Lane procedure

The external Flash component must be in read mode at reset. Usually, this is true for most

parallel NOR devices.

2.7

USB 2.0 Host ports (UHC)

SPEAr320S provides two USB 2.0 Host ports with integrated PHYs.

Main features:

●

Each port can be independently configured for high-speed mode (USB 2.0, up to

480 Mbps); in this case, the corresponding controller is programmed according to

standard EHCI specifications.

●

Each port can be independently configured for full-speed mode (USB 1.1, up to

12 Mbps) or low-speed mode (USB 1.1, up to 1.5 Mbps); in this case, the

corresponding controller is programmed according to standard OHCI specifications.

●

Internal 2 KB FIFO queues

●

Internal DMA support

●

Dedicated output control signals to manage external power switches

●

Dedicated input signals to sense any over-current condition detected by external power

switches

NAND02GW3A

Micron

2 Gb

256 MB

2048 + 64 bytes

K9F2G08V0A

Samsung

2 Gb

256 MB

512 + 16 bytes

NAND04GW3B2BN6

Micron

4 Gb

512 MB

2048 + 64 bytes

K9F4G08V0A

Samsung

4 Gb

512 MB

512 + 16 bytes

NAND08GW3B2CN6

Micron

8 Gb

1 GB

2048 + 64 bytes

K9K8G08V0A

Samsung

8 Gb

1 GB

512 + 16 bytes

K9F8G08V0M

Samsung

8 Gb

1 GB

512 + 16 bytes

Table 2.

NAND Flash devices supported by the BootROM firmware (continued)

Part number

Vendor

Density

Capacity

Bus

width

Page size

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