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SPEAR320S-2 Folha de dados(PDF) 71 Page - STMicroelectronics |
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SPEAR320S-2 Folha de dados(HTML) 71 Page - STMicroelectronics |
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71 / 113 page ![]() SPEAr320S Electrical characteristics Doc ID 022508 Rev 2 71/113 This implies: Cext = (CL-CS)*2 Example: For this example, a Rakon XTAL003342 24 MHz oscillator has been used. For the Rakon XTAL003342 crystal, CL = 12 pF With CS = ~3 pF, we have: Cext = CL1 = CL2 = 18 pF MCLK generated from an external clock source Table 41. MCLK external user clock source characteristics Symbol Parameter Conditions Min Typ Max Unit fMCLK_XI External clock source frequency No limitation 24(1) 33 MHz VMCLK_XIH MCLK_XI input pin high level voltage MCLK_VDD2V5 - 0.3 MCLK_VDD2V5 V VMCLK_XIL MCLK_XI input pin low level voltage MCLK_GNDSUB 0.3 V DuCy(MCLK_XI) Duty cycle (2) 40 60 % tr(MCLK_XI) tf(MCLK_XI) MCLK_XI input rise and fall time -5% of the clock period +5% of the clock period % CIN(MCLK_XI) MCLK_XI input capacitance 7pF IL(MCLK_XI) MCLK_XI input leakage current MCLK_GNDSUB ≤V IN ≤ MCLK_VDD2V5 ±1µA 1. A frequency of 24 MHz is mandatory to obtain the required operating frequency for all clocks generated by the USB PLL (PLL3). 2. An initial delay of 1 µs + 2048 fMCLK_XI cycles occurs for duty cycle detection and internal clock availability. |
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