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SPEAR320S-2 Folha de dados(PDF) 82 Page - STMicroelectronics

Nome de Peças SPEAR320S-2
Descrição Electrónicos  Embedded MPU with ARM926 core for industrial and consumer applications
PDF  113 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR320S-2 Folha de dados(HTML) 82 Page - STMicroelectronics

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Timing requirements
SPEAr320S
82/113
Doc ID 022508 Rev 2
5.5.2
DDR2/LPDDR write cycle timing characteristics
Figure 11.
DDR2/LPDDR write cycle waveform
5.5.3
DDR2/LPDDR command timing characteristics
Figure 12.
DDR2/LPDDR command waveform
Table 54.
DDR2/LPDDR write cycle timing requirements
Symbol
Description
Min
Max
Unit
tDQSS
Positive DQS latching edge to associated CK edge
-0.5
0.5
ns
tDS
DQ & DQM output setup time relative to DQS
0
0.25tCK – 0.76
tDH
DQ & DQM output hold time relative to DQS
0
0.25tCK – 0.84
DDR_MEM_DQS_#
DDR_MEM_DQ_#
DDR_MEM_CLKP/
DDR_MEM_CLKN
tDS
tDH
tDH
tDS
tDS
tDH
t DQSS
Table 55.
DDR2/LPDDR command timing requirements
Symbol
Description
Min
Max
Unit
tIS
Address and control output setup time
0
0.5tCK – 0.5
ns
tIH
Address and control output hold time
0
0.5tCK – 0.59
tIS
tIH
CLK
Address and
commands



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