PIC16C72 datasheet(20/288 Pages) MICROCHIP

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PIC16C7X

DS30390E-page 20

FIGURE 4-3:

PIC16C76/77 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

1FFFh

Stack Level 2

Page 0

Page 1

Page 2

Page 3

07FFh

0800h

0FFFh

1000h

17FFh

1800h

On-Chip

4.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

RP1:RP0 (STATUS<6:5>)

= 00

→ Bank0

= 01

→ Bank1

= 10

→ Bank2

= 11

→ Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

4.2.1

GENERAL PURPOSE REGISTER FILE

The register ﬁle can be accessed either directly, or indi-

rectly

through

the

File

Select

FSR

(Section 4.5).

Applicable Devices

72 73 73A 74 74A 76 77

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