PIC16C72 datasheet(59/288 Pages) MICROCHIP

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DS30390E-page 59

PIC16C7X

7.0

TIMER0 MODULE

The Timer0 module timer/counter has the following fea-

tures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simpliﬁed block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In counter mode, Timer0 will increment

either on every rising or falling edge of pin RA4/T0CKI.

The incrementing edge is determined by the Timer0

Applicable Devices

72 73 73A 74 74A 76 77

Source Edge Select bit T0SE (OPTION<4>). Clearing

bit T0SE selects the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 7.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler assignment is controlled in software by control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, ...,

1:256 are selectable. Section 7.3 details the operation

of the prescaler.

7.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overﬂows from FFh to 00h. This overﬂow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module interrupt ser-

vice routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP since the timer is shut off during SLEEP. See

Figure 7-4 for Timer0 interrupt timing.

Applicable Devices

72 73 73A 74 74A 76 77

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt

ﬂag bit T0IF

on overﬂow

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0+1

T0+2

NT0

NT0+1

NT0+2

MOVWF TMR0

MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

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