P4C164LL-100CWCLF datasheet(6/10 Pages) PYRAMID

6 / 10 page

P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM

Page 6

Document # SRAM116 REV 04

AC TEST COnDITIOnS

TRUTH TABLE

TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED)(6)

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

Mode

I/O

Power

Standby

High Z

Standby

High Z

Standby

OUT Disabled

High Z

Active

Read

OUT

Active

Write

High Z

Active

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

note:

Because of the ultra-high speed of the P4C164LL, care must be taken

whentestingthisdevice;aninadequatesetupcancauseanormalfunction-

ing part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

CC and ground planes

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V

CC and ground. To avoid signal reflections,

proper termination must be used; for example, a 50Ω test environment

should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at

the comparator input, and a 589Ω resistor must be used in series with

OUT to match 639Ω (Thevenin Resistance).

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