5

LTC1291

CC

HARA TERISTICS

A

TYPICALPERFOR

CE

Maximum Clock Rate vs Source

Resistance

Maximum Filter Resistor vs

Cycle Time

CYCLE TIME (µs)

10

100

1k

10k

10

1k

10k

1291 G12

1

100

+

–

100

0.2

0.4

0.6

0.8

1.0

1k

10k

100k

1291 G11

0

CLK = 1MHz

+

–

+IN

–IN

AMBIENT TEMPERATURE (°C)

–50

0

100

300

400

500

1000

700

–10

30

50

130

1291 G14

200

800

900

600

–30

10

70

90 110

ON CHANNEL

OFF CHANNEL

GUARANTEED

Input Channel Leakage Current

vs Temperature

Sample-and-Hold Acquisition

Time vs Source Resistance

* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK

FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE

ERROR AT ANY CODE TRANSITION FROM ITS 1MHz

VALUE IS FIRST DETECTED.

VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE

DETECTED.

PI FU CTIO S

#

PIN

FUNCTION

DESCRIPTION

1

CS

Chip Select Input

A logic low on this input enables the LTC1291.

2, 3

CH0, CH1

Analog Inputs

These inputs must be free of noise with respect to GND.

4

GND

Analog Ground

GND should be tied directly to an analog ground plane.

Digital Data Input

The multiplexer address is shifted into this input.

Digital Data Output

The A/D conversion result is shifted out of this output.

7

CLK

Shift Clock

This clock synchronizes the serial data transfer.

Positive Supply and

This pin provides power and defines the span of the A/D converter. This supply must be kept free of noise and

Reference Voltage

ripple by bypassing directly to the analog ground plane.

AMBIENT TEMPERATURE (°C)

–50

150

200

250

50

1291 G10

100

0

–25

0

25

75

125

100

50

MSB-FIRST DATA

LSB-FIRST DATA

100

1

10

100

1k

10k

1291 G13

+

–

0V TO 5V INPUT STEP