LTC1291 datasheet(12/20 Pages) LINER

12 / 20 page

LTC1291

STAA

$102A

LOAD DUMMY DIN INTO SPI,

START SCK

WAIT3 LDAA

$1029

CHECK SPI STATUS REG

BPL

WAIT3

CHECK IF TRANSFER IS DONE

BSET

$08,X#$01

D0 GOES HIGH (CS GOES HIGH)

LDAA

$102A

LOAD LTC1291 LSBs IN ACC

STAA

$63

STORE LSBs IN $63

JMP

LOOP

START NEXT CONVERSION

Interfacing to the Parallel Port of the Intel 8051 Family

The Intel 8051 has been chosen to show the interface

between the LTC1291 and parallel port microprocessors.

Usually the signals CS, DIN and CLK are generated on three

port lines and the DOUT signal is read on a fourth port line.

LDAA

$1029

CHECK SPI STATUS REG

WAIT1 BPL

WAIT1

CHECK IF TRANSFER IS DONE

LDAA

$51

LOAD DIN INTO ACC A FROM $51

STAA

$102A

LOAD DIN INTO SPI, START SCK

WAIT2 LDAA

$1029

CHECK SPI STATUS REG

BPL

WAIT2

CHECK IF TRANSFER IS DONE

LDAA

$102A

LOAD LTC1291 MSBs INTO ACC A

STAA

$62

STORE MSBs IN $62

LDAA

$52

LOAD DUMMY DIN INTO ACC A

FROM $52

LABEL MNEMONIC

OPERAND

COMMENTS

LABEL MNEMONIC

OPERAND

COMMENTS

Timing Diagram for Interface to Intel 8051

Hardware and Software Interface to Intel 8051

LTC1291 AI09

DOUT FROM LTC1291 STORED IN 8051 RAM

B10

B11

LSB

MSB

CLK

DOUT

ANALOG

INPUTS

P1.4

P1.3

8051

DIN

P1.2

MUX ADDRESS

A/D RESULT

LTC1291

CH0

CH1

This works very well. One can save a line by tying the DIN

and DOUT lines together. The 8051 first sends the start bit

and MUX Address to the LTC1291 over the line connected

to P1.2. Then P1.2 is reconfigured as an input and the 8051

reads back the 12-bit A/D result over the same data line.

CLK

DATA

(DIN/DOUT)

LTC1291 AI08

PS BIT LATCHED

INTO LTC1291

8051 P1.2 OUTPUT DATA

TO LTC1291

8051 P1.2 RECONFIGURED

AS INPUT AFTER THE 5TH RISING

CLK BEFORE THE 5TH FALLING CLK

LTC1291 SENDS A/D RESULT

BACK TO 8051 P1.2

LTC1291 TAKES CONTROL OF DATA

LINE ON 5TH FALLING CLK

START

B11

SGL/

DIFF

ODD/

SIGN

MSBF

B10 B9

B3 B2

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