AT25DF081A datasheet(35/54 Pages) ETC2

35 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

11.2 Write Status Register Byte 1

The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform

a Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued,

the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical

“1”.

To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the opcode of 01h must

be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a

don’t care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two addi-

tional don’t care bits (see Table 11-3). Any additional data bytes that are sent to the device will be ignored. When

the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Regis-

ter will be reset back to a logical “0”. The values of bits five, four, three, and two and the state of the SPRL bit

before the Write Status Register Byte 1 command was executed (the prior state of the SPRL bit) will determine

whether or not a Global Protect or Global Unprotect will be performed. Please refer to “Global Protect/Unprotect”

on page 21 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin

must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,

the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL

bit in the Status Register will be reset back to the logical “0” state.

If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL

bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and

the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logi-

cal “0”, the WP pin must be deasserted.

Figure 11-2. Write Status Register Byte 1

Table 11-3.

Write Status Register Byte 1 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPRL

Global Protect/Unprotect

SCK

MSB

0000000

OPCODE

10 11

814 15

MSB

DXD

STATUS REGISTER IN

BYTE 1

HIGH-IMPEDANCE

AT25DF081A Folha de dados(PDF) 35 Page - List of Unclassifed Manufacturers

AT25DF081A Folha de dados(HTML) 35 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Folha de dados Download

Ligação URL