AT25DF081A datasheet(30/54 Pages) ETC2

30 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

10.5 Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the max-

imum clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted and

the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes

must be clocked in to specify the starting address location of the first byte to read within the OTP Security Register.

Following the three address bytes, two dummy bytes must be clocked into the device before data can be output.

After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP

Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has

been read, the device will continue reading back at the beginning of the register (000000h). No delays will be

incurred when wrapping around from the end of the register to the beginning of the register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS

pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 10-5. Read OTP Security Register

SCK

MSB

01110111

410 11

812

31 32

29 30

OPCODE

AAAA

AAA

MSB

DDDDDDD

ADDRESS BITS A23-A0

MSB

XXXXX

DON'T CARE

DATA BYTE 1

HIGH-IMPEDANCE

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