AT25DF081A datasheet(15/54 Pages) ETC2

15 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

8.3

Block Erase

A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one

of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode

of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase

command can be started, the Write Enable command must have been previously issued to the device to set the

WEL bit of the Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must

be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address

within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device

will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the

block is internally self-timed and should take place in a time of tBLKE.

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded

by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values

can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte

erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded

by the device, the complete three address bytes must still be clocked into the device before the CS pin is deas-

serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the

device will abort the operation and no erase operation will be performed.

If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked

down state, then the Block Erase command will not be executed, and the device will return to the idle state once

the CS pin has been deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an

incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory

location within the region to be erased is protected or locked down.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the

device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the

tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL

bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop-

erly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.

Figure 8-5.

Block Erase

SCK

MSB

CCCCCCCC

410 11

812

29 30

27 28

OPCODE

AAAA

AAA

ADDRESS BITS A23-A0

HIGH-IMPEDANCE

AT25DF081A Folha de dados(PDF) 15 Page - List of Unclassifed Manufacturers

AT25DF081A Folha de dados(HTML) 15 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Folha de dados Download

Ligação URL