PIC10F320T-EMCSQTP datasheet(18/210 Pages) MICROCHIP

18 / 210 page

PIC10(L)F320/322

DS41585A-page 18

Preliminary

 2011 Microchip Technology Inc.

Bank 0 (Continued)

20h

PMADRL

PMADR<7:0>

0000 0000

21h

PMADRH

—

PMADR8

---- ---0

22h

PMDATL

PMDAT<7:0>

xxxx xxxx

uuuu uuuu

23h

PMDATH

—

—PMDAT<13:8>

--xx xxxx

--uu uuuu

24h

PMCON1

—

CFGS

LWLO

FREE

WRERR

WREN

1000 0000

1000 q000

25h

PMCON2

Program Memory Control Register 2 (not a physical register)

0000 0000

26h

CLKRCON

—CLKROE

—

-0-- ----

27h

NCO1ACCL

NCO1 Accumulator <7:0>

0000 0000

28h

NCO1ACCH

NCO1 Accumulator <15:8>

0000 0000

29h

NCO1ACCU

—

NCO1 Accumulator <19..16>

---- 0000

2Ah

NCO1INCL

NCO1 Increment <7:0>

0000 0001

2Bh

NCO1INCH

NCO1 Increment <15:8>

0000 0000

2Ch

—

Unimplemented

—

2Dh

NCO1CON

N1EN

N1OE

N1OUT

N1POL

—

—N1PFM

0000 ---0

00x0 ---0

2Eh

NCO1CLK

N1PWS<2:0>

—

—N1CKS<1:0>

000- --00

2Fh

Reserved

xxxx xxxx

uuuu uuuu

30h

WDTCON

—

—WDTPS<4:0>

SWDTEN

--01 0110

31h

CLC1CON

LC1EN

LC1OE

LC1OUT

LC1INTP

LC1INTN

LC1MODE<2:0>

00x0 -000

32h

CLC1SEL0

—

LC1D2S<2:0>

—

LC1D1S<2:0>

-xxx -xxx

-uuu -uuu

33h

CLC1SEL1

—

LC1D4S<2:0>

—

LC1D3S<2:0>

-xxx -xxx

-uuu -uuu

34h

CLC1POL

LC1POL

—

LC1G4POL LC1G3POL

LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

35h

CLC1GLS0

LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T

LC1G1D2N

LC1G1D1T

LC1G1D1N xxxx xxxx uuuu uuuu

36h

CLC1GLS1

LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T

LC1G2D2N

LC1G2D1T

LC1G2D1N xxxx xxxx uuuu uuuu

37h

CLC1GLS2

LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T

LC1G3D2N

LC1G3D1T

LC1G3D1N xxxx xxxx uuuu uuuu

38h

CLC1GLS3

LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T

LC1G4D2N

LC1G4D1T

LC1G4D1N xxxx xxxx uuuu uuuu

39h

CWG1CON0

G1EN

G1OEB

G1OEA

G1POLB

G1POLA

—

G1CS0

0000 0--0

3Ah

CWG1CON1

G1ASDLB<1:0>

G1ASDLA<1:0>

—

G1IS<1:0>

xxxx --xx

uuuu --uu

3Bh

CWG1CON2

G1ASE

G1ARSEN

—

G1ASDCLC1 G1ASDFLT xx-- --xx uu-- --uu

3Ch

CWG1DBR

—

—CWG1DBR<5:0>

--xx xxxx

--uu uuuu

3Dh

CWG1DBF

—

—CWG1DBF<5:0>

--xx xxxx

--uu uuuu

3Eh

VREGCON

—

—VREGPM1

Reserved

---- --01

3Fh

BORCON

SBOREN

BORFS

—

BORRDY

10-- ---q

uu-- ---u

TABLE 2-3:

SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other resets

Legend:

= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note

Unimplemented, read as ‘1’.

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