PIC10F320T-EMCSQTP datasheet(84/210 Pages) MICROCHIP

84 / 210 page

PIC10(L)F320/322

DS41585A-page 84

Preliminary

 2011 Microchip Technology Inc.

TABLE 11-1:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0

R/W-0/0

—

IOCAF3

IOCAF2

IOCAF1

IOCAF0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS - Bit is set in hardware

bit 7-4

Unimplemented

: Read as ‘0’.

bit 3-0

IOCAF<3:0>:

Interrupt-on-change PORTA Flag bits

= An enable change was detected on the associated pin.

Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling

edge was detected on RAx.(1)

= No change was detected, or the user cleared the detected change.

Note 1:

Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

IOCAF

—

IOCAF3

IOCAF2

IOCAF1

IOCAF0

IOCAN

—

IOCAN3

IOCAN2

IOCAN1

IOCAN0

IOCAP

—

IOCAP3

IOCAP2

IOCAP1

IOCAP0

TRISA

—

—(1)

TRISA2

TRISA1

TRISA0

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.

Note 1:

Unimplemented, read as ‘1’.

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